This information is from Adrian's RojakPot (http://www.rojakpot.com/default.aspx?location=1) which is a highly recommended site. Please read the below information from the site, not on these forums. The text of the memory subsystem settings is reproduced here only because anecdotal evidence indicates the site has disappeared off the DNS world at times and his work is too important to lose! This chap has obviously spent months developing the information and you owe it to him to read it on his site and trigger his advertising revenue........
Click Here to Read the Full Guide (http://www.rojakpot.com/default.aspx?location=1).
TL. :cool:
****************Archive Info Only******************
Act Bank A to B CMD Delay
Common Options : 2 Cycles, 3 Cycles
Quick Review
This BIOS feature specifies the minimum amount of time between successive ACTIVATE commands to the same DDR device. The shorter the delay, the faster the next bank can be activated for read or write operations. However, because row activation requires a lot of current, using a short delay may cause excessive current surges.
For desktop PCs, a delay of 2 cycles is recommended as current surges aren't really important. The performance benefit of using the shorter 2 cycles delay is of far greater interest. The shorter delay means every back-to-back bank activation will take one clock cycle less to perform. This improves the DDR device's read and write performance.
Switch to 3 cycles only when there are stability problems with the 2 cycles setting.
Delay DRAM Read Latch
Common Options : Auto, No Delay, 0.5ns, 1.0ns, 1.5ns
Quick Review
This feature is similar to the DRAM Read Latch Delay BIOS feature. It fine-tunes the DRAM timing parameters to adjust for different DRAM loadings.
The DRAM load changes with the number as well as the type of memory modules installed. DRAM loading increases as the number of memory modules increases. It also increases if you use double-sided modules instead of single-sided ones. In short, the more DRAM devices you use, the greater the DRAM loading.
With heavier DRAM loads, you may need to delay the moment when the memory controller latches onto the DRAM device during reads. Otherwise, the memory controller may fail to latch properly onto the desired DRAM device and read from it.
The Auto option allows the BIOS to select the optimal amount of delay from values preset by the manufacturer.
The No Delay option forces the memory controller to latch onto the DRAM device without delay, even if the BIOS presets indicate that a delay is required.
The three timing options (0.5ns, 1.0ns and 1.5ns) give you manual control of the read latch delay.
Normally, you should let the BIOS select the optimal amount of delay from values preset by the manufacturer (using the Auto option). But if you notice that your system has become unstable upon installation of additional memory modules, you should try setting the DRAM read latch delay yourself.
The amount of delay should just be enough to allow the memory controller to latch onto the DRAM device in your particular situation. Don't unnecessarily increase the delay. Start with 0.5ns and work your way up until your system stabilizes.
If you have a light DRAM load, you can ensure optimal performance by manually using the No Delay option. If your system becomes unstable after using the No Delay option, simply revert back to the default value of Auto so that the BIOS can adjust the read latch delay to suit the DRAM load.
DRAM Act to PreChrg CMD
Common Options : 5T, 6T, 7T, 8T
Quick Review
This BIOS feature controls the memory bank's minimum row active time (tRAS). This constitutes the length of time from the activate command to the precharge command of the same bank.
Now, tRAS is important because it determines how soon after a row activation can the same row be precharged for another cycle. If an exceedingly long tRAS is chosen, the row may be unnecessarily delayed from precharging for another cycle. But if you set it for too short a period, there may not be enough time to complete the read/write cycle. When that happens, data may be lost or corrupted.
For optimal performance, use the lowest value you can (5T in this case). But if you start getting memory errors or system crashes, increase the value one clock cycle at a time until you get a stable system.
Please note that because the bank cycle time (tRC) = minimum row active time (tRAS) + row precharge time (tRP), you should take into account the values for tRC and tRP before selecting the tRAS value.
DRAM Data Integrity Mode
Common Options : ECC, Non-ECC
Quick Review
This BIOS feature controls the ECC feature of the memory controller.
ECC, which stands for Error Checking and Correction, enables the memory controller to detect and correct single-bit soft memory errors. The memory controller will also be able to detect double-bit errors although it will not be able to correct them. This provides increased data integrity and system stability. However, this feature can only be enabled if you are using special ECC memory modules.
Because present day processors use 64-bit wide data paths, 72-bit (64-bit data + 8-bit ECC) ECC memory modules are required to implement ECC. Please note that the maximum data transfer rate of the 72-bit ECC memory module is the same as the 64-bit memory module. The extra 8-bits are only for the ECC code and do not carry any data. So, using 72-bit memory modules will not give you any boost in performance.
In fact, because the memory controller has to calculate the ECC code for every data word that is read or written, there will be some performance degradation, roughly in the region of 3-5%. This is one of the reasons why ECC memory modules are not popular among desktop users. Throw in the fact that ECC memory modules are both expensive and hard to come by; and you have the top three reasons why ECC memory modules will never be mainstream solutions.
If you are using standard 64-bit memory modules, you must select the Non-ECC option.
But if you have already forked out the the money for 72-bit ECC memory modules, you should enable the ECC feature, no matter what people say about losing some memory performance. It doesn't make sense to buy expensive ECC memory modules and then disable ECC! Remember, you are not really losing performance. You are just trading it for greater stability and data integrity.
DRAM Idle Timer
Common Options : 0T, 8T, 16T, 64T, Infinite, Auto
Quick Review
This BIOS feature sets the number of idle cycles that is allowed before the memory controller forces such open pages to close and precharge.
The premise behind this BIOS feature is the concept of temporal locality. According to this concept, the longer the open page is left idle, the less likely it will be accessed again before it needs to be precharged. Therefore, it would be better to prematurely close and precharge the page so that it can be opened quickly when a data request comes along.
It can be set to a variety of clock cycles from 0T to 64T. This sets the number of clock cycles the open pages are allowed to idle before they are closed and precharged. There's also an Infinite option as well as an Auto option.
If you select 0 Cycle, then the memory controller will immediately precharge the open pages as soon as there's an idle cycle.
If you select Infinite, the memory controller will never precharge the open pages prematurely. The open pages will be left activated until they have to be precharged.
If you select Auto, the memory controller will use the manufacturer's preset default setting.
Most manufacturers use a default value of 8T which allows the memory controller to precharge the open pages once eight idle cycles have passed.
For general desktop use, it is recommended that you choose the Infinite option so that precharging can be delayed for as long as possible. This reduces the number of refreshes and increases the effective memory bandwidth.
For applications (i.e. servers) that perform a lot of random accesses, it is advisable that you select 0T as subsequent data requests would most likely be fulfilled by other pages. Closing open pages to precharge will prepare those pages for the next data request that hits them. There's also the added benefit of increased data integrity due to more frequent refreshes.
DRAM Interleave Time
Common Options : 0ms, 0.5ms
Quick Review
This BIOS feature determines the amount of additional delay between successive bank accesses when the SDRAM Bank Interleave feature has been enabled. Naturally, the shorter the delay, the faster the memory module can switch between banks and consequently perform better.
Therefore, it is recommended that you set the DRAM Interleave Time as low as possible for better memory performance. In this case, it would be 0ms which introduces no additional delay between bank accesses. Increase the DRAM Interleave Time to 0.5ms only if you experience instability with the 0ms setting.
DRAM PreChrg to Act CMD
Common Options : 2T, 3T
Quick Review
This BIOS feature controls the memory bank's precharge time (tRP). This constitutes the time it takes for the Precharge command to complete and the row to be available for activation.
Now, tRP is important because it determines how soon a row can be activated after a Precharge command has been issued. If an exceedingly long tRP is chosen, that may unnecessarily reduce performance by preventing the row from being activated earlier. But if you set it for too short a period, the row may not be sufficiently precharged and that may cause data loss or corruption when the memory controller attempts to read from that row.
For optimal performance, use the lowest value you can (2T in this case). But if you start getting memory errors or system crashes, increase the value.
Please note that because the bank cycle time (tRC) = minimum row active time (tRAS) + row precharge time (tRP), you should take into account the values for tRC and tRAS before selecting the tRP value.
DRAM Ratio (CPU:DRAM)
Common Options : 1:1, 3:2, 3:4, 4:5, 5:4
Quick Review
The choice of options in this BIOS feature depends entirely on the setting of the DRAM Ratio H/W Strap or N/B Strap CPU As BIOS feature.
When DRAM Ratio H/W Strap has been set to Low, the available options are 1:1 and 3:4.
When DRAM Ratio H/W Strap has been set to High, the available options are 1:1 and 4:5.
When N/B Strap CPU As has been set to PSB800, the available options are 1:1, 3.2 and 5:4.
When N/B Strap CPU As has been set to PSB533, the available options are 1:1 and 4:5.
When N/B Strap CPU As has been set to PSB400, the only available option is 3:4.
The options of 1:1, 3:2, 3:4 and 4:5 refer to the available CPU-to-DRAM (or CPU:DRAM) ratios.
Please note that while the Pentium 4 processor is said to have a 400MHz or 533MHz or 800MHz FSB (front side bus), the front side bus (also known as CPU bus) is actually only running at 100MHz or 133MHz or 200MHz respectively. This is because the Pentium 4 bus is a Quad Data Rate or QDR bus which transfers four times as much data as a single data rate bus.
For marketing reasons, the Pentium 4 bus is labeled as running at 400MHz or 533MHz or 800MHz when it is actually running at only 100MHz, 133MHz and 200MHz respectively. It is important to keep this in mind when setting this BIOS feature.
For example, if you set a 3:2 ratio with a 200MHz (800MHz QDR) CPU bus, the memory bus will run at (200MHz / 3) x 2 = 133MHz or 266MHz DDR.
By default, this BIOS feature is set to By SPD. This allows the chipset to query the SPD (Serial Presence Detect) chip on every memory module and use the appropriate ratio.
It is recommended that you select the ratio that allows you to maximize your memory modules' capabilities. But bear in mind that synchronous operation using the 1:1 ratio is also highly desirable as it allows a high throughput.
DRAM Ratio H/W Strap
Common Options : High, Low, By CPU
Quick Review
This BIOS feature allows you to circumvent the CPU-to-DRAM ratio limitation found in the newer Intel i845-series of chipsets. In those chipsets, Intel has chosen to limit the choices of available CPU-to-DRAM ratios.
When a 400MHz FSB processor is installed, the choices of CPU-to-DRAM ratio are limited to 1:1 or 3:4.
When a 533MHz FSB processor is installed, the choices of CPU-to-DRAM ratio are limited to 1:1 or 4:5.
Fortunately, this BIOS feature allows you to circumvent that limitation.
The DRAM Ratio H/W Strap BIOS feature actually controls the setting of the external hardware reset strap assigned to the MCH (Memory Controller Hub) of the chipset. By setting it High or Low, you can trick the chipset into thinking that the 400MHz FSB or the 533MHz FSB is being used.
When this BIOS feature is set to High, you will be able to access the 533MHz CPU-to-DRAM ratios of 1:1 and 4:5.
When this BIOS feature is set to Low, you will be able to access the 400MHz CPU-to-DRAM ratios of 1:1 and 3:4.
By default, this BIOS feature is set to By CPU, whereby the hardware strap will be set according to the actual FSB rating of the processor.
Generally, you do not need to manually adjust the hardware strap setting. But if you require access to the CPU-to-DRAM ratio that would normally not be available to you, then this BIOS feature would be very helpful indeed.
DRAM Read Latch Delay
Common Options : Enabled, Disabled
Quick Review
This BIOS feature is similar to the Delay DRAM Read Latch BIOS feature. It fine-tunes the DRAM timing parameters to adjust for different DRAM loadings.
The DRAM load changes with the number as well as the type of memory modules installed. DRAM loading increases as the number of memory modules increases. It also increases if you use double-sided modules instead of single-sided ones. In short, the more DRAM devices you use, the greater the DRAM loading.
With heavier DRAM loads, you may need to delay the moment when the memory controller latches onto the DRAM device during reads. Otherwise, the memory controller may fail to latch properly onto the desired DRAM device and read from it.
The Auto option allows the BIOS to select the optimal amount of delay from values preset by the manufacturer.
The No Delay option forces the memory controller to latch onto the DRAM device without delay, even if the BIOS presets indicate that a delay is required.
The three timing options (0.5ns, 1.0ns and 1.5ns) give you manual control of the read latch delay.
Normally, you should let the BIOS select the optimal amount of delay from values preset by the manufacturer (using the Auto option). But if you notice that your system has become unstable upon installation of additional memory modules, you should try setting the DRAM read latch delay yourself.
The amount of delay should just be enough to allow the memory controller to latch onto the DRAM device in your particular situation. Don't unnecessarily increase the delay. Start with 0.5ns and work your way up until your system stabilizes.
If you have a light DRAM load, you can ensure optimal performance by manually using the No Delay option. If your system becomes unstable after using the No Delay option, simply revert back to the default value of Auto so that the BIOS can adjust the read latch delay to suit the DRAM load.
OS Select For DRAM > 64MB
Common Options : OS/2, Non-OS/2
Details
Quick Review
This BIOS feature determines how systems with more than 64MB of memory are managed. A wrong setting can cause problems like erroneous memory detection.
If you are using an older version of the IBM OS/2 operating system, you should select OS/2.
If you are using the IBM OS/2 Warp v3.0 or higher operating system, you should select Non-OS/2.
If you are using an older version of the IBM OS/2 operating system but have already installed all the relevant IBM FixPaks, you should select Non-OS/2.
Users of non-OS/2 operating systems (like Microsoft Windows XP) should select the Non-OS/2 option.
OS/2 Onboard Memory > 64M
Common Options : Enabled, Disabled
Quick Review
This is similar to the OS Select For DRAM > 64M BIOS feature.
This BIOS feature determines how systems with more than 64MB of memory are managed. A wrong setting can cause problems like erroneous memory detection.
If you are using an older version of the IBM OS/2 operating system, you should select Yes.
If you are using the IBM OS/2 Warp v3.0 or higher operating system, you should select No.
If you are using an older version of the IBM OS/2 operating system but have already installed all the relevant IBM FixPaks, you should select No.
Users of non-OS/2 operating systems (like Microsoft Windows XP) should select the No option.
SDRAM Idle Limit
Common Options : Disabled, 0 Cycle, 8 Cycles, 12 Cycles, 16 Cycles, 24 Cycles, 32 Cycles, 48 Cycles
Quick Review
This BIOS feature sets the number of idle cycles that is allowed before the memory controller forces such open pages to close and precharge.
The premise behind this BIOS feature is the concept of temporal locality. According to this concept, the longer the open page is left idle, the less likely it will be accessed again before it needs to be precharged. Therefore, it would be better to prematurely close and precharge the page so that it can be opened quickly when a data request comes along.
It can be set to a variety of clock cycles from 0 Cycle to 48 Cycles. This sets the number of clock cycles the open pages are allowed to idle before they are closed and precharged. There's also a Disabled option.
If you select 0 Cycle, then the memory controller will immediately precharge the open pages as soon as there's an idle cycle.
If you select Disabled, the memory controller will never precharge the open pages prematurely. The open pages will be left activated until they have to be precharged.
The default value is 8 cycles which allows the memory controller to precharge the open pages once eight idle cycles have passed.
For general desktop use, it is recommended that you disable this feature so that precharging can be delayed for as long as possible. This reduces the number of refreshes and increases the effective memory bandwidth.
For applications (i.e. servers) that perform a lot of random accesses, it is advisable that you select 0 Cycle as subsequent data requests would most likely be fulfilled by other pages. Closing open pages to precharge will prepare those pages for the next data request that hits them. There's also the added benefit of increased data integrity due to more frequent refreshes.
SDRAM Tras Timing Value
Common Options : 2, 3, 4, 5, 6, 7, 8, 9
Quick Review
This BIOS feature controls the memory bank's minimum row active time (tRAS). This constitutes the length of time from the activate command to the precharge command of the same bank.
Now, tRAS is important because it determines how soon after a row activation can the same row be precharged for another cycle. If an exceedingly long tRAS is chosen, the row may be unnecessarily delayed from precharging for another cycle. But if you set it for too short a period, there may not be enough time to complete the read/write cycle. When that happens, data may be lost or corrupted.
For optimal performance, use the lowest value you can (usually 5 clock cycles). But if you start getting memory errors or system crashes, increase the value one clock cycle at a time until you get a stable system.
Please note that because the bank cycle time (tRC) = minimum row active time (tRAS) + row precharge time (tRP), you should take into account the values for tRC and tRP before selecting the tRAS value.
SDRAM Trp Timing Value
Common Options : 1, 2, 3, 4
Quick Review
This BIOS feature controls the memory bank's precharge time (tRP). This constitutes the time it takes for the Precharge command to complete and the row to be available for activation.
Now, tRP is important because it determines how soon a row can be activated after a Precharge command has been issued. If an exceedingly long tRP is chosen, that may unnecessarily reduce performance by preventing the row from being activated earlier. But if you set it for too short a period, the row may not be sufficiently precharged and that may cause data loss or corruption when the memory controller attempts to read from that row.
For optimal performance, use the lowest value you can (usually 2 clock cycles). But if you start getting memory errors or system crashes, increase the value.
Please note that because the bank cycle time (tRC) = minimum row active time (tRAS) + row precharge time (tRP), you should take into account the values for tRC and tRAS before selecting the tRP value.
Sorry for using your thread TL, just found this intersting for the thread.. corsair has made a little presentation for those who wanna know some more about how ram works..
http://www.corsairmicro.com/corsair/produc...3707/index.html (http://www.corsairmicro.com/corsair/products/tech/memory_basics/153707/index.html)
No apologies required Kreg, it's a community thread (and old) and meant for your use!
TL.