Dead Men Walking

http://www.aoaforums.com/forum/showthread.php?t=19005 (http://www.aoaforums.com/forum/showthread.php?t=19005)

You figure it out.  :D

You have to read it twice to get it.  :rolleyes: I was giggling like a loon by the end of that thread. Oi! TeaLeaf, come over here and explain this one will you.

:blink:

its simple, they said latency is usually used to measure the delay between memory transactions yes?

well this tras or tcas (cant remember) latency setting is missleading, as its the duration of a 'write/read' from memory.  If your trying to write blocks of x num of bits to memory and can only write so many bits per cycle then you need to make sure this setting is long enough to allow the entire write/read..... else the operation is split into two and read/write ops have an overhead.... hence do it in one go not many gos.

Got that?  :D

QuoteOriginally posted by Stryker@Sep 26 2003, 01:16 PM
its simple, they said latency is usually used to measure the delay between memory transactions yes?

well this tras or tcas (cant remember) latency setting is missleading, as its the duration of a 'write/read' from memory.  If your trying to write blocks of x num of bits to memory and can only write so many bits per cycle then you need to make sure this setting is long enough to allow the entire write/read..... else the operation is split into two and read/write ops have an overhead.... hence do it in one go not many gos.

Got that?  :D

I've got new socks.  :D

Alrighty, I'll have a stab at this as I'm bored right now.  Stryker's beaten me to it while I've been typing this, but I'll post this up anyway.  Anyone feel free to correct if I've got something wrong.

To start somewhere simple: All those memory timing numbers are the ones you set in your BIOS to control how fast your processor can access the memory chips on the DIMMs you slot in the motherboard.  All amounts are in 'numbers of front-side bus clock cycles'.

You can lower these in your BIOS, if your memory can handle it, if you want to tweak things to run a bit quicker.  So if you see the memory timings 7-3-3-2.5, the numbers mean - in this order:

tRAS
Minimum bank active to precharge command.  In other words, number of clocks it takes to open and close an address row in memory.  The cycle time of memory (tRC), time between consecutive accesses at different row addresses, is given by tRAS + tRP.

tRP
Minimum row precharge time.

tRCD
RAS to CAS delay. Amount of clock cycles needed by the memory after it's recieived the row address, before the processor can send the column address.

tCAS
CAS Latency.  Number of clock cycles after the memory receives the column address that data is available at the memory pins to be read/written by the processor.

For a simplified memory read/write access we're interested in tRAS, tRCD, and tCAS.  Clock cycles needed to set up the row address, clock cycles needed to set up the column address, and the amount of clock cycles after the column address that data can be read/written.

To try and explain those a bit, you need to know that DRAM (of any type) is arranged as a matrix of rows and columns.  You need a row address and a column address to access any one particular location.  (It's done like this to cut down on the amount of physical address signals you need to wire to the chip, as you just multiplex the row and column address on the same lines. Anyway - it's not all that important, and I don't want to lose you, just yet :) )

Getting back to timings.  Take, for instance, two PC2700 DDR memory modules: a standard one with timings of 7-3-3-2.5, and a premium overclockers one at 6-2-2-2.  Run them both using the same (front-side bus) clock speed, and the system running on the overclockers memory should be quicker overall because the numbers of clock cycles needed to access the data are lower.  This is called latency.  Lower latency should, in theory, mean a quicker system.

What the chaps in the original thread are saying is that (for their nForce2 boards) the traditional overclocking view of trying to reduce memory latencies, to improve overall system performance, isn't as effective as they first thought.

By paring down their tRAS time to improve their overall latencies, they're actually slowing their systems down because memory can't supply the data to the processor at the speeds specified in the BIOS.  Especially when you're doing some hefty overclocking.  What a processor will do if a bus cycle terminates early is retry the access again.  When it's retrying a lot of accesses, your system slows down.  Hence their book analogy.

1) You look at a page in a book (processor accesses a row address in memory)
2) You find the first line on the page (processor accesses the column in memory)
3) You start reading that line (processor accesses the data at the memory address)
4) *BAM* someone shuts the book in your face (memory can't finish supplying the data, because tRAS is set too low and processor has started addressing the next access)
5) You then have to reopen the book, find the right page and line, and finish reading that line (processor has to retry the whole access to get the data it needed)

This is a very simplified view, and I hope it makes sense.  The observation made in Sadako's link, originally comes from the DIMM manufacturer Mushkin, who say that to avoid having the processor retry accesses on an nForce2 board you need to set the tRAS memory timing to:

tRAS = tRCD + tCAS + 2 (rounded up to the next whole integer)

So for someone who has 7-3-3-2.5 timings, they should really be adjusted to 8-3-3-2.5 (3 + 2 + 2.5 = 7.5, round up to 8 ) or higher.  Most seem to getting optimal results with tRAS of 11, though I've no idea why.

Results also seem to vary from system to system.  So, unless you're really after top notch performance, are overclocking to the max, and are prepared to benchmark a lot to see if there's any improvement - I wouldn't worry about doing it as you probably won't 'see' any difference, other than in benchmarks.

I might have a go though :P

Cadaver, you sad ............... NOBODY CARES!

QuoteOriginally posted by OldBloke+Sep 26 2003, 01:42 PM-->